1. Field of the Invention
The present invention relates to non-volatile NOR-type memory strings. In particular, the present invention relates manufacturing processes for the 3-dimensional structure of such a non-volatile NOR-type memory string.
2. Discussion of the Related Art
In high density 3-dimensional memory structures, such as those disclosed in the Copending Application, it is desirable to include a metal sublayer shunt which is electrically connected to either a source sublayer or a drain sublayer. Both sources and drains may be contacted by a conductive sublayer shunt (i.e., as separate conductive sublayers). For example, in the process illustrated in FIG. 5a of the Copending Application, conductive sublayers may be deposited in addition to source sublayer 521, drain sublayer 523, sacrificial sublayer 522 (which would subsequently be replaced by a channel sublayer). These sublayers are deposited one sublayer at a time and then patterned using photoresist and etched. In this detailed description, the drain, source and channel or sacrificial sublayers, including any associated conductive sublayers, are collectively referred to as the “active layer” and a number of active layers provided one on top of another, separated from one another by a dielectric layer, are referred to as a “NIN stack.”
The metal sublayers are provided to achieve significantly reduced resistance in each of the source and drain sublayers. A lower resistance corresponds to a lower resistance-capacitance (RC) time constant, which results in a higher speed device. For this purpose, it is desirable to achieve low resistance using thick metal-comprising conductive sublayers.
Conductive sublayers having a metal (e.g., tungsten) that can withstand the subsequent elevated temperature processing (>500° C.) are difficult to etch in 3-D memory structures because of etch selectivity. That is, the etch rate of the conductive layer may not be significantly greater than the etch rate of the photoresist and/or hard mask that are used to protect other features that are not to be etched. (In general, to protect the material not intended to be etched, the target material should etch at a significantly faster rate than the masking layer or layers. It would be undesirable that the masking layer or layers are completely removed before etching of the target material is complete.) Etch selectivity becomes an even greater problem as each metal sublayer becomes thicker, as a greater number of metal sublayers are present in the stack (e.g. metal shunt sublayers are provided in both source and drain sublayers), and as more memory layers (e.g., 8 or 16 layers of active strips) are provided. However, to achieve higher density at lower cost, it is desirable to provide 8 or more memory layers.
Another problem encountered in fabrication of these memory structures is their mechanical stability, due to their high aspect ratios. (In this regard, the aspect ratio is the ratio between the structure's height to its width). It has been shown that a semiconductor structure with a high aspect ratio can be mechanically unstable, so that the structure leand or even topples completely during the fabrication process.